Design News is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Chip Design Software Turns to AI to Relieve Throughput Bottleneck

Article-Chip Design Software Turns to AI to Relieve Throughput Bottleneck

Black Kira/Getty Images GettyImagesaichipdesign.jpg
AI is remaking EDA software into a faster, more data-driven tool for chip and system design.
EDA companies are incorporating AI algorithms into their design software to speed functions such as pc board design, verification, and simulation, and build a rich database for future design iterations.

Electronic design automation (EDA) software is inthe midst of a major evolution as artificial intelligence (AI) is gradually being phased into many design tools to relieve the traditional bottlenecks in chip and system design.  

Engineering design tasks such as pc board layout, verification, simulation, and data management are using machine learning algorithms to speed these data-intensive tasks. The hope is that time-consuming functions such as debugging complex designs can see improved throughput, freeing design engineers for higher-level tasks.

At the same time, the use of AI is expected to help create a wealth of useful design data that will enable engineers to perform subsequent design iterations faster and more efficiently, without the need to reinvent the wheel.

Siemens’ Questa Speeds Verification

The challenges of today’s electronics systems design were spelled out by Darron May, Product Manager, VM, Debug and Coverage for design software supplier Siemens. The company has introduced a data-driven verification tool, called Questa Verification IQ.

“ICs are ever-more complex,” May said during a recent interview with Design News. Citing a recent Wilson Research Study May said, “With ASICs, 70% of the time is spent on functional verification. Only 24% achieve first-time silicon success, and only a third of the projects finish on time.”

The design bottleneck is equally sobering for field-programmable gate arrays (FPGAs), May noted from the research study, with only 16% of designs achieving zero bug escapes.

Image courtesy of Wilson ResearchWilson Research says ASIC and FPGA design cycles continue to run late and experience many design bugs.

A Wilson Research study done for Siemens found that ASIC and FPGA design cycles continue to run late and experience many design bugs.

AI Leverages Big Data

May said that harnessing data was the key to improvement. Using AI algorithms, Questa Verification IQ unifies coverage data from the formal and simulation engines within Siemens’ Questa™ platform, OneSpin® software, Symphony™ platform for analog and mixed-signal simulation, as well as Siemens’ Veloce™ hardware for emulation and prototyping. The machine learning functionality in Questa Verification IQ then analyzes the data to predict patterns and holes, identify root causes, and prescribe solutions to potential issues; thereby helping to improve efficiency and giving teams the information needed to signoff with confidence.

Questa Verification IQ provides a platform that automatically captures all data from every engine run across the life of a project, helping customers manage requirements, coding, testing and release management across the design and verification process.

“This tool integrates with our simulation and verification tools,” May said. “It provides insight into verification by extracting data to monitor progress.

Cadence's Optimality Reduces Repeated Simulations

Rival design software company Cadence Design Tools is also incorporating AI into its tool to improve design productivity. Last year, the company introduced its Optimality Intelligent System Explorer tool, an AI-driven Multiphysics Design Analysis and Optimization tool which Cadence claims provides 10X faster design closure with fewer simulations than the traditional human-intensive approach. The tool is designed to maintain accuracy from the IC to the package and out through the board.

Cadence VP Ben Gu discusses the Optimality tool in this short video:

According to Cadence, the Optimality Intelligent System Explorer tool enables designers to quickly determine optimum electrical performance, avoiding suboptimal local minima and maxima, while mapping variations for additional consideration and exploration of the complete design space.

Cadence is using Optimality Intelligent System Explorer  to improve the performance of its Clarity 3D Solver for 3D electromagnetic (EM) analysis and Sigrity X technologies for high-speed signal integrity (SI) and power integrity (PI) analyses.

“With electromagnetic and signal integrity analysis, Optimality allows us to perform intelligent sweeps and find optimized results more quickly,” said Brad Griffin, Product Management, Group Director at Cadence Design Systems.

Cadence has also designed an AI-driven verification platform called Verisum, which leverage big data and AI across multiple runs of multiple engines throughout an entire SoC verification campaign. The Verisium platform optimizes verification workloads, boosts coverage, and accelerates root cause analysis of bugs. 

Synopsys Sees Success With AI Tools

Another design software company, Synopsys, has been using AI algorithms for several years in its Synopsys.dso.ai autonomous design system. The company recently announced it has registered 100 commercial tape-outs with this tool, with many customers reporting significant productivity increases and reductions in power consumption and die size.

“The tool provides a creative reinforcement path to provide an optimization tool that works in conjunction with design tools,” said Stelios Diamantidis, Senior Director and Distinguished Architect, Synopsys Autonomous Design Solutions, in a recent interview with Design News.

The tool enables engineers to define objectives and parameters and feed in data. Synopsys.dso.ai then optimizes the design, cutting overall design time and effort.

The following video describes some features of Synopsys.dso.ai:

According to Diamantidis, Synopsys focused its efforts on speeding physical design functions such as place-and-route. “Over the years, there have been many improvements in verification tools, but physical design has been slower to improve. AI-based solutions are the ideal applications space for machine-based reinforcement learning, the value is very profound.”

Diamantidis added the physical design is an area where experience is often the best teacher. “Physical design is an area of very high expertise, that is why there is shortage of physical design expertise. Using an AI-based tool can help capture key design information for reuse in subsequent physical designs. Synopsys.dso.ai shares expertise and accelerates convergence, guiding users in the right direction.”

While high performance designs have benefitted from the tool, Diamantidis noted that the software has found a number of applications. “We have customers that used Synopsys.dso.ai to help design image sensors in IoT systems. Other applications include autonomous vehicles and consumer electronics.”

Spencer Chin is a Senior Editor for Design News covering the electronics beat. He has many years of experience covering developments in components, semiconductors, subsystems, power, and other facets of electronics from both a business/supply-chain and technology perspective. He can be reached at [email protected]

Hide comments
account-default-image

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish